This invention relates to programmable logic devices, and more particularly to programmable logic devices having improved interconnections between adjacent columns of logic array blocks.
Programmable logic devices, which are integrated circuits that can be selectively configured to provide customized logic functions, are well known. Such devices contain many relatively simple logic elements that are interconnected using both fixed and programmable connections. The performance ultimately attained by a programmable logic device is closely related to both the sophistication of the individual logic element building blocks that are used and the capacity of the device to flexibly interconnect this logic. These two resources must be carefully balanced so that the device is capable of being programmed to perform the logic functions that are required without becoming excessively costly or becoming too slow during operation.
Some programmable logic devices contain regions of logic known as logic array blocks, which contain multiple subgroups of logic referred to as "macrocells". In addition to the interconnections within each block for interconnecting the macrocells, global horizontal and vertical conductors and additional programmable interconnections are provided to interconnect the logic array blocks. Commonly-assigned U.S. Pat. No. 5,371,422, describes a programmable logic device of this type that is flexible enough to efficiently implement a wide variety of logic designs. However, some logic designs could be implemented even more efficiently if programmable interconnections of greater flexibility were available.
It is therefore an object of the present invention to provide more flexible interconnections between logic circuit elements in a programmable logic array device.
It is a further object of the present invention to provide improved interconnections that allow macrocell outputs in adjacent columns of logic array blocks to be more readily connected to horizontal conductors.